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mos integrated circuit m pd78062(a), 78063(a), 78064(a) 8-bit single-chip microcontroller the mark shows major revised points. the information in this document is subject to change without notice. description the m pd78062(a), 78063(a), and 78064(a) are products to which a quality assurance program more stringent than that used for the m pd78062, 78063, and 78064 (standard models) is applied (nec classifies these products as special quality grade models). m pd78062(a), 78063(a), and 78064(a) are products in the m pd78064 subseries within the 78k/0 series, which incorporate lcd controller/driver, 8-bit resolution a/d converter, timer, serial interface, interrupt functions and many other peripheral hardwares. various development tools are also provided. for the details of functional description, refer to the following user's manual.be sure to read this manual before designing your system. m pd78064 78064y subseries user's manual : u10105e 78k/0 series user's manual (instruction : ieu-1372 features large on-chip rom & ram note under planning minimum instruction execution time can be varied from high speed (0.4 m s) to ultra-low speed (122 m s) i/o ports: 57 (including segment signal output dual-function pins) lcd controller/driver supply voltage v dd = 2.0 to 6.0 v (static display mode) v dd = 2.5 to 6.0 v (1/3 bias) v dd = 2.7 to 6.0 v (1/2 bias) 8-bit resolution a /d converter : 8 channels serial interface : 2 channels timer: 5 channels supply voltage : v dd = 2.0 to 6.0 v item program memory data memory product name (rom) internal high-speed ram lcd display ram m pd78062(a) 16k bytes 512 bytes m pd78063(a) 24k bytes 40 4 bits m pd78064(a) 32k bytes package 1024 bytes 100-pin plastic qfp (fine pitch) (14 14mm, 0.5 mm pitch) 100-pin plastic qfp (14 20 mm, 0.65 mm pitch) 100-pin plastic lqfp note (fine pitch) (14 14 mm, 0.5 mm pitch) document no. u10335ej2v0ds00 (2nd edition) date published august 1997 n printed in japan 1997 data sheet
2 m pd78062(a), 78063(a), 78064(a) applications control units of automobile electronic systems, gas detectors and circuit breakers, various safety systems, hemadynamometers, etc. ordering information part number package m pd78062gc(a)- -7ea 100-pin plastic qfp (fine pitch) (14 14 mm, resin thickness: 1.45 mm) m pd78062gc(a)- -8eu note 100-pin plastic lqfp (fine pitch) (14 14 mm, resin thickness: 1.40 mm) m pd78062gf(a)- -3ba 100-pin plastic qfp (14 20mm) m pd78063gc(a)- -7ea 100-pin plastic qfp (fine pitch) (14 14 mm, resin thickness: 1.45 mm) m pd78063gc(a)- -8eu note 100-pin plastic lqfp (fine pitch) (14 14 mm, resin thickness: 1.40 mm) m pd78063gf(a)- -3ba 100-pin plastic qfp (14 20mm) m pd78064gc(a)- -7ea 100-pin plastic qfp (fine pitch) (14 14 mm, resin thickness: 1.45 mm) m pd78064gc(a)- -8eu note 100-pin plastic lqfp (fine pitch) (14 14 mm, resin thickness: 1.40 mm) m pd78064gf(a)- -3ba 100-pin plastic qfp (14 20mm) note under planning caution the m pd78062gc(a), 78063gc(a), and 78064gc(a) are available in two types of packages (refer to 12. package drawings). for the available packages, consult nec. remark indicates a rom code suffix. quality grade special differences between m pd78062(a), 78063(a) and 78064(a), and m pd78062, 78063 and 78064 product name m pd78062(a), 78063(a), 78064(a) m pd78062, 78063, 78064 item quality grade special standard please refer to "quality grades on nec semiconductor devices" (document no. c11531e) published by nec corporation to know the specification of quality grade on the devices and its recommended applications.
3 m pd78062(a), 78063(a), 78064(a) 78k/0 series development the following shows the 78 k/0 series products development. subseries names are shown inside frames. note under planning 64-pin 64-pin 64-pin 64-pin 80-pin 80-pin emi noise reduction version of the pd78054. uart and d/a converter were added to the pd78014, and i/o was enhanced. pd78054 pd78054y pd78058f pd78058fy pd780034 pd780024 pd780964 pd780924 pd780034y pd780024y m m m m m m m m m m 64-pin an a/d converter of the pd780024 was enhanced. serial i/o of the pd78018f was enhanced, emi noise reduction version. on-chip inverter control circuit and uart, emi noise reduction version. m m m m an a/d converter of the pd780924 was enhanced. m pd78044f pd78044h 80-pin 80-pin pd78064 pd78064b pd780308 100-pin 100-pin 100-pin pd780308y pd78064y pd78098 80-pin pd78p0914 64-pin 78k/0 series n-ch open drain input/output was added to the pd78044f, display output total: 34 basic subseries for driving fip, display output total: 34 lcd drive sio of the pd78064 was enhanced, and rom and ram were expanded. emi noise reduced version of the pd78064. basic subseries for driving lcds, on-chip uart. iebus tm supported an iebus controller was added to the pd78054. lv on-chip pwm output, lv digital code decoder, and hsync counter. m m m m m m m m m m m m m m m m pd78083 pd78002 pd78002y pd780001 pd78014 pd78014y pd78018f pd78018fy low-voltage (1.8 v) operation versions of the pd78014 with several rom and ram capacities available. an a/d converter and 16-bit timer were added to the pd78002. an a/d converter was added to the pd78002. basic subseries for control. on-chip uart, capable of operating at a low voltage (1.8 v). m m m m m m m m 42/44-pin 64-pin 64-pin 64-pin 64-pin pd78014h m emi noise reduction version of pd78018f. m m pd780058 pd780058y note m m 80-pin serial i/o of the pd78054 was enhanced, emi noise reduction version. 100-pin 100-pin products in mass production products under development y subseries products are compatible with i 2 c bus. a timer was added to the pd78054, and the external interface function was enhanced. rom-less versions of the pd78078. pd78070a pd78070ay m pd78078 pd78078y pd780018ay m m m m m 100-pin serial i/o of the pd78078y was enhanced, and only selected functions are provided. m m 100-pin control pd78075b pd78075by m m emi noise reduction version of the pd78078. m inverter control pd780228 100-pin the i/o and fip c/d of the pd78044h were enhanced, display output total: 48 m m m pd780208 100-pin fip tm drive the i/o and fip c/d of the pd78044f were enhanced, display output total: 53 m m pd780208 m pd78098b emi noise reduction version of the pd78098. m 80-pin m meter control pd780973 on-chip automobile meter driving controller/driver. m 80-pin
4 m pd78062(a), 78063(a), 78064(a) the following table shows the differences among subseries functions. function rom timer 8-bit 10-bit 8-bit serial interface i/o v dd min. external subseries name capacity 8-bit 16-bit watch wdt a/d a/d d/a value expansion control m pd78075b 32 k to 40 k 4ch 1ch 1ch 1ch 8ch C 2ch 3ch (uart: 1ch) 88 1.8 v available m pd78078 48 k to 60 k m pd78070a C 61 2.7 v m pd780058 24 k to 60 k 2ch 2ch 3ch (time division uart: 1ch) 68 1.8 v m pd78058f 48 k to 60 k 3ch (uart: 1ch) 69 2.7 v m pd78054 16 k to 60 k 2.0 v m pd780034 8 k to 32 k C 8ch C 3ch (uart: 1ch, 51 1.8 v m pd780024 8ch C time division 3-wire: 1ch) m pd78014h 2ch 53 m pd78018f 8 k to 60 k m pd78014 8 k to 32 k 2.7 v m pd780001 8 k C C 1ch 39 C m pd78002 8 k to 16 k 1ch C 53 available m pd78083 C 8ch 1ch (uart: 1ch) 33 1.8 v C inverter m pd780964 8 k to 32 k 3ch note C 1ch C 8ch C 2ch (uart: 2ch) 47 2.7 v available control m pd780924 8ch C fip m pd780208 32 k to 60 k 2ch 1ch 1ch 1ch 8ch C C 2ch 74 2.7 v C drive m pd780228 48 k to 60 k 3ch C C 1ch 72 4.5 v m pd78044h 32 k to 48 k 2ch 1ch 1ch 68 2.7 v m pd78044f 16 k to 40 k 2ch lcd m pd780308 48 k to 60 k 2ch 1ch 1ch 1ch 8ch C C 3ch (time division uart: 1ch) 57 2.0 v C drive m pd78064b 32 k 2ch (uart: 1ch) m pd78064 16 k to 32 k iebus m pd78098b 40 k to 60 k 2ch 1ch 1ch 1ch 8ch C 2ch 3ch (uart: 1ch) 69 2.7 v available supported m pd78098 32 k to 60 k meter control m pd780973 24 k to 32 k 3ch 1ch 1ch 1ch 5ch C C 2ch (uart: 1ch) 56 4.5 v C lv m pd78p0914 32 k 6ch C C 1ch 8ch C C 2ch 54 4.5 v available note 10-bit timer: 1 channel
5 m pd78062(a), 78063(a), 78064(a) functional outline 16k bytes 24k bytes 32k bytes 512 bytes 1024 bytes 40 4 bits 8 bits 32 registers (8 bits 8 registers 4 banks) on-chip minimum instruction execution time cycle modification function 0.4 m s/0.8 m s/1.6 m s/3.2 m s/6.4 m s/12.8 m s (at 5.0 mhz operation) 122 m s (at 32.768 khz operation) ? 16-bit operation ? multiplication/division (8 bits 8 bits,16 bits ? 8 bits) ? bit manipulation (set, reset, test, boolean operation) ? bcd correction, etc. total : 57 ? cmos input : 0 2 ? cmos i/o : 55 ? 8-bit resolution 8 channels ? segment signal output : maximum 40 ? common signal output : maximum 4 ? bias : 1/2 or 1/3 switchable ? 3-wire serial i/o/sbi/2-wire serial i/o mode selectable : 1 channel ? 3-wire serial i/o/uart mode selectable : 1 channel ? 16-bit timer/event counter : 1 channel ? 8-bit timer/event counter : 2 channels ? watch timer : 1 channel ? watchdog timer : 1 channel 3 (14-bit pwm output capability : 1) 19.5 khz, 39.1 khz, 78.1 khz, 156 khz, 313 khz, 625 khz, 1.25 mhz, 2.5 mhz, 5.0 mhz (at main system clock 5.0 mhz operation) 32.768 khz (at subsystem clock 32.768 khz operation) 1.2 khz, 2.4 khz, 4.9 khz, 9.8 khz (at main system clock 5.0 mhz operation) internal : 12, external : 6 internal : 1 1 internal: 1, external: 1 v dd = 2.0 to 6.0 v ? 100-pin plastic qfp (fine pitch) (14 14 mm, resin thickness: 1.45 mm) ? 100-pin plastic qfp (14 20 mm) ? 100-pin plastic lqfp (fine pitch) (14 14 mm, resin thickness: 1.40 mm, under planning) rom high-speed ram lcd display ram m pd78064(a) m pd78063(a) m pd78062(a) instruction set lcd controller/driver serial interface timer internal memory when main system clock selected when subsystem clock selected i/o ports (including segment signal output pins) a/d converter vectored interrupt sources package maskable non-maskable softwar item product name general registers minimum instruction execution time timer output clock output buzzer output test input supply voltage
6 m pd78062(a), 78063(a), 78064(a) contents 1. pin configuration (top view) ........................................................................................................ 7 2. block diagram ................................................................................................................................... 10 3. pin functions ...................................................................................................................................... 11 3.1 port pins .......................................................................................................................................................... 11 3.2 other pins ........................................................................................................................................................ 13 3.3 pin i/o circuits and recommended connection of unused pins ............................................................. 14 4. memory space ..................................................................................................................................... 18 5. peripheral hardware function feature ............................................................................... 19 5.1 port ................................................................................................................................................................... 19 5.2 clock generator .............................................................................................................................................. 20 5.3 timer/event counter ....................................................................................................................................... 20 5.4 clock output control circuit ......................................................................................................................... 23 5.5 buzzer output control circuit ....................................................................................................................... 23 5.6 a/d converter .................................................................................................................................................. 24 5.7 serial interface ............................................................................................................................................... 24 5.8 lcd controller/driver ..................................................................................................................................... 26 6. interrupt functions and test functions ............................................................................... 27 6.1 interrupt functions ......................................................................................................................................... 27 6.2 test functions ................................................................................................................................................. 31 7. standby function ............................................................................................................................. 32 8. reset function .................................................................................................................................. 32 9. instruction set ................................................................................................................................. 33 10. electrical specifications ............................................................................................................ 35 11. characteristic curves (reference values) ......................................................................... 56 12. package drawings ........................................................................................................................... 58 13. recommended soldering conditions ....................................................................................... 61 appendix a. development tools ....................................................................................................... 62 appendix b. related documents ....................................................................................................... 64
7 m pd78062(a), 78063(a), 78064(a) 1. pin configuration (top view) ? 100-pin plastic qfp (fine pitch)(14 14 mm, resin thickness: 1.45 mm) m pd78062gc(a)- -7ea, 78063gc(a)- -7ea, 78064gc(a)- -7ea ? 100-pin plastic lqfp (fine pitch)(14 14 mm, resin thickness: 1.40 mm) m pd78062gc(a)- -8eu note , 78063gc(a)- -8eu note , 78064gc(a)- -8eu note p11/ani1 p10/ani0 98 99 100 97 96 95 94 93 92 91 90 89 88 87 av ss p117 p116 p115 p114 p113 p112 p111 p110 p05/intp5 p04/intp4 p03/intp3 p02/intp2 86 85 84 83 82 p01/intp1/ti01 p00/intp0/ti00 reset xt2 xt1/p07 v dd 1 p12/ani2 p13/ani3 2 3 p14/ani4 4 p15/ani5 5 p16/ani6 6 p17/ani7 7 av dd 8 av ref 9 p100 10 p101 11 v ss 12 p102 13 p103 14 p30/to0 15 p31/to1 16 p32/to2 17 p33/ti1 18 19 20 p34/ti2 p35/pcl 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 45 s13 44 43 42 41 s12 s11 s10 s9 s8 s7 s6 s5 s4 s3 s2 s1 s0 v ss v lc2 v lc1 v lc0 bias com3 p36/buz 21 p37 22 com0 23 24 25 com1 com2 50 s18 49 48 47 46 s17 s16 s15 s14 p27/sck0 72 73 74 75 70 71 69 68 67 66 65 64 63 62 61 60 59 58 57 56 p70/si2/r x d p26/so0/sb1 p25/si0/sb0 p80/s39 p81/s38 p82/s37 p83/s36 p84/s35 p85/s34 p86/s33 p87/s32 p90/s31 p91/s30 p92/s29 p93/s28 p94/s27 p95/s26 p96/s25 p97/s24 55 54 53 52 51 s23 s22 s21 s20 s19 80 79 78 77 76 x1 x2 ic p72/sck2/asck p71/so2/t x d 81 note under planning cautions 1. connect directly the ic (internally connected) pin to v ss . 2. connect the av dd pin to v dd . 3. connect the av ss pin to v ss .
8 m pd78062(a), 78063(a), 78064(a) ? 100-pin plastic qfp (14 20 mm) m pd78062gf(a)- -3ba, 78063gf(a)- -3ba m pd78064g(a)- -3ba cautions 1. connect directly the ic (internally connected) pin to v ss . 2. connect the av dd pin to v dd . 3. connect the av ss pin to v ss . p26/so0/sb1 p25/si0/sb0 98 99 100 97 96 95 94 93 92 91 90 89 88 87 p80/s39 p81/s38 p82/s37 p83/s36 p84/s35 p85/s34 p86/s33 p87/s32 p90/s31 p91/s30 p92/s29 p93/s28 p94/s27 86 85 84 83 82 p95/s26 p96/s25 p97/s24 s23 s22 s21 1 p27/sck0 p70/si2/r x d 2 3 p71/so2/t x d 4 p72/sck2/asck 5 ic 6 x2 7 x1 8 v dd 9 xt1/p07 10 xt2 11 reset 12 p00/intp0/ti00 13 p01/intp1/ti01 14 p02/intp2 15 p03/intp3 16 p04/intp4 17 p05/intp5 18 19 p110 20 p111 p112 21 p113 22 p114 23 24 25 p115 p116 81 26 p117 av ss 27 p10/ani0 28 p11/ani1 29 30 p12/ani2 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 50 49 48 47 46 p37 p36/buz p35/pcl p34/ti2 p33/ti1 p32/to2 p31/to1 p30/to0 p103 p102 v ss p101 p100 av ref av dd p17/ani7 p16/ani6 p15/ani5 p14/ani4 p13/ani3 77 78 79 80 75 76 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 s20 s19 s18 s17 s16 s15 s14 s13 s12 s11 s10 s9 s8 s7 s6 s5 p4 s3 s2 s1 s0 v ss v lc2 v lc1 v lc0 bias com3 com2 com1 com0
9 m pd78062(a), 78063(a), 78064(a) ani0-ani7 : analog input p110-p117 : port11 asck : asynchronous serial clock pcl : programmable clock av dd : analog power supply reset : reset av ref : analog reference voltage r x d : receive data avss : analog ground s0-s39 : segment output bias : lcd power supply bias control sb0-sb1 : serial bus buz : buzzer clock si0, si2 : serial input com0-com3 : common output so0, so2 : serial output ic : internally connected sck0, sck2 : serial clock intp0-intp5 : interrupt from peripherals ti00, ti01 : timer input p00-p05, p07 : port0 ti1, ti2 : timer input p10-p17 : port1 to0-to2 : timer output p25-p27 : port2 t x d : transmit data p30-p37 : port3 v dd : power supply p70-p72 : port7 v lc0 -v lc2 : lcd power supply p80-p87 : port8 v ss : ground p90-p97 : port9 x1, x2 : crystal (main system clock) p100-p103 : port10 xt1, xt2 : crystal (subsystem clock)
10 m pd78062(a), 78063(a), 78064(a) 2. block diagram to0/p30 16-bit timer/ event counter ti00/intp0/p00 ti01/intp1/p01 to1/p31 8-bit timer/ event counter 1 ti1/p33 to2/p32 8-bit timer/ event counter 2 ti2/p34 watchdog timer watch timer si0/sb0/p25 serial interface 0 so0/sb1/p26 sck0/p27 si2/rxd/p70 serial interface 2 so2/txd/p71 sck2/asck/p72 av dd a/d converter av ss av ref ani0/p10- ani7/p17 interrupt control intp0/p00- intp5/p05 buzzer output buz/p36 clock output control pcl/p35 p00 port0 p01-p05 p07 port1 p10-p17 port11 p110-p117 port2 p25-p27 port3 p30-p37 port7 p70-p72 port8 p80-p87 port9 p90-p97 port10 p100-p103 lcd controller/ driver s0-s23 bias f lcd reset x1 x2 xt1/p07 xt2 78k/0 cpu core rom ram system control v dd v ss ic s24/p97- s31/p90 s32/p87- s39/p80 com0-com3 v lc0 -v lc2 remark the internal rom and ram capacities differ depending on the product .
11 m pd78062(a), 78063(a), 78064(a) 3. pin functions 3.1 port pins (1/2) dual- function pin pin name i/o input only port 1 8-bit input/output port. input/output can be specified bit-wise. when used as an input port, on-chip pull-up resistor can be used in software. note2 input to0 to1 to2 ti1 ti2 pcl buz si2/rxd so2/txd sck2/ asck p25 p26 p27 p30 p31 p32 p33 p34 p35 p36 p37 port 7 3-bit input/output port. input/output can be specified bit-wise. when used as an input port, on-chip pull-up resistor can be used in software. p00 p01 p02 p03 p04 p05 p07 note1 p10 to p17 input input only input intp0/ti00 intp1/ti01 intp2 intp3 intp4 intp5 xt1 ani0 to ani7 input p70 p71 p72 function after reset input input input input input port 3 8-bit input/output port. input/output can be specified bit-wise. when used as an input port, on-chip pull-up resistor can be used in software. input/ output input/ output port 2 3-bit input/output port. input/output can be specified bit-wise. when used as an input port, on-chip pull-up resistor can be used in software. input/ output input/ output input/output can be specified bit-wise. when used as an input port, on-chip pull-up resistor can be used in software. port 0 7-bit i/o port. input/ output notes 1. when using the p07/xt1 pins as an input port, set (1) bit 6 (frc) of the processor clock control register (pcc) (the on-chip feedback resistor of the subsystem clock oscillator should not be used). 2. when using the p10/ani0 to p17/ani7 pins as the a/d converter analog input, port 1 is set to input mode. however, on-chip pull-up resistor is not automatically used. so0/sb1 si0/sb0 sck0
12 m pd78062(a), 78063(a), 78064(a) 3.1 port pins (2/2) dual- function pin pin name i/o port 8 8-bit input/output port input/output can be specified bit-wise. when used as an input port , on-chip pull-up resistor can be used in software. input/output port/segment signal output function can be specified in 2-bit unit by the lcd control register (lcdc). after reset port 10 4-bit input/output port input/output can be specified bit-wise. when used as an input port, on-chip pull-up resistor can be used in software. led direct drive capability. port 11 8-bit input/output port input/output can be specified bit-wise. when used as an input port, on-chip pull-up resistor can be used in software. falling edge detection capability. port 9 8-bit input/output port input/output can be specified bit-wise. when used as an input port, on-chip pull-up resistor can be used in software. input/output port/segment signal output function can be specified in 2-bit unit by the lcd control register (lcdc). function p80 to p87 input/ output input s39 to s32 s31 to s24 input input/ output p90 to p97 input/ output p100 to p103 input input/ output p110 to p117 input
13 m pd78062(a), 78063(a), 78064(a) 3.2 other pins (1/2) intp0 intp1 intp2 intp3 intp4 intp5 si0 si2 so0 so2 sb0 sb1 sck0 sck2 rxd txd asck ti00 ti01 ti1 ti2 to0 to1 to2 pcl buz s0 to s23 s24 to s31 s32 to s39 com0 to com3 v lc0 to v lc2 bias p00/ti00 p01/ti01 p02 p03 p04 p05 p25/sb0 p70/rxd p26/sb1 p71/txd p25/si0 p26/so0 p27 p72/asck p70/si2 p71/so2 p72/sck2 p00/intp0 p01/intp1 p33 p34 p30 p31 p32 p35 p36 p97 to p90 p87 to p80 dual- function pin pin name i/o function after reset input output serial interface serial data output. input serial interface serial data input. external interrupt request input by which the effective edge (rising edge, falling edge, or both rising edge and falling edge) can be specified. serial interface serial data input/output. input /output input output input input input /output serial interface serial clock input/output. output output output output output asynchronous serial interface serial data input. asynchronous serial interface serial data output. asynchronous serial interface serial clock input. external count clock input to 16-bit timer (tm0). capture trigger signal input to capture register (cr00). external count clock input to 8-bit timer (tm1). external count clock input to 8-bit timer (tm2). 16-bit timer (tm0) output (shared with 14-bit pwm output). input input input input input input input input input input input input output input output clock output (for main system clock, subsystem clock trimming). buzzer output. lcd controller/driver segment signal output. lcd controller/driver common signal output. lcd drive voltage. split resistors can be incorporated by mask option. lcd drive power supply. 8-bit timer (tm1) output. 8-bit timer (tm2) output.
14 m pd78062(a), 78063(a), 78064(a) 3.2 other pins (2/2) a/d converter analog input. a/d converter reference voltage input. a/d converter analog power supply. connect to v dd . a/d converter ground potential. connect to v ss . system reset input. main system clock oscillation crystal connection. subsystem clock oscillation crystal connection. positive power supply. ground potential. internal connection. connect directly to v ss pin. pin name i/o ani0 to ani7 av ref av dd av ss reset x1 x2 xt1 xt2 v dd v ss ic input function after reset dual- function pin p10 to p17 p07 input 3.3 pin i/o circuits and recommended connection of unused pins the input/output circuit type of each pin and recommended connection of unused pins are shown in table 3-1. for the input/output circuit configuration of each type, refer to figure 3-1 . table 3-1. input/output circuit type of each pin (1/2) p00/intp0/ti00 p01/intp1/ti01 p02/intp2 p03/intp3 p04/intp4 p05/intp5 p07/xt1 p10/ani0 to p17/ani7 p25/si0/sb0 p26/so0/sb1 p27/sck0 p30/to0 p31/to1 p32/to2 connected to v ss . connected to v dd . input input/output input input/output 2 8-a 16 11 10-a 5-a pin name i/o recommended connection when not used input/output circuit type input input input input input independently connected to v dd or v ss through resistor. independently connected to v ss through resistor.
15 m pd78062(a), 78063(a), 78064(a) i/o recommended connection when not used pin name input/output circuit type 8-a 5-a 8-a 5-a 8-a 17-a 5-a 8-a 17 18 2 16 table 3-1. input/output circuit type of each pin (2/2) p33/ti1 p34/ti2 p35/pcl p36/buz p37 p70/si2/rxd p71/so2/txd p72/sck2/asck p80/s39 to p87/s32 p90/s31 to p97/s24 p100 to p103 p110 to p117 s0 to s23 com0 to com3 v lc0 to v lc2 bias reset xt2 av ref av dd av ss ic leave open. leave open. connected to v ss . connected to v dd . connected to v ss . connected directly to v ss . output input independently connected to v dd or v ss through resistor. input/output independently connected to v dd through resistor.
16 m pd78062(a), 78063(a), 78064(a) in type 2 type 5-a type 8-a type 11 type 16 type 10-a schmitt-triggered input with hysteresis characteristic pull-up enable data output disable p-ch in/out v dd v dd p-ch n-ch pull-up enable data output disable input enable p-ch in/out v dd v dd p-ch n-ch figure 3-1. pin input/output circuits (1/2) pull-up enable data output disable p-ch in/out v dd v dd p-ch n-ch open drain pull-up enable data output disable input enable p-ch in/out v dd v dd p-ch n-ch n-ch v ref + p-ch (threshold voltage) comparator feedback cut-off p-ch xt1 xt2
17 m pd78062(a), 78063(a), 78064(a) figure 3-1. pin input/output circuits (2/2) type 17 type 18 type 17-a out p-ch n-ch p-ch n-ch p-ch n-ch v lc0 v lc1 v lc2 seg data p-ch n-ch p-ch n-ch p-ch n-ch v lc0 v lc1 v lc2 com data n-ch p-ch out pull-up enable data output disable input enable p-ch in/out v dd v dd p-ch n-ch p-ch n-ch p-ch n-ch p-ch n-ch v lc0 v lc1 v lc2 seg data
18 m pd78062(a), 78063(a), 78064(a) m pd78062(a) 3fffh fd00h m pd78063(a) 5fffh m pd78064(a) 7fffh 4. memory space the memory map of m pd78062(a)/78063(a)/78064(a) is shown in figure 4-1. figure 4-1. memory map note the internal rom and internal high-speed ram capacities differ depending on the product. (refer to the following table.) fb00h last address of internal rom start address of internal high-speed ram nnnnh mmmmh product name ffffh ff00h feffh mmmmh mmmmh-1 fee0h fa80h fa7fh fa58h fa57h nnnnh+1 nnnnh 0000h nnnnh 0fffh 0800h 07ffh 0080h 007fh 0040h 003fh 0000h use prohibited use prohibited program area callf entry area program area callt table area vector table area general registers 32 8 bits internal high-speed ram note lcd display ram 40 4 bits program memory space data memory space special function register (sfr) 256 8 bits 1000h internal rom note
19 4 m pd78062(a), 78063(a), 78064(a) 5. peripheral hardware function feature 5.1 port there are two kinds of i/o port. cmos input (p00, p07) : 2 cmos input/output (p01 to p05, port 1 to 3, 7 to 11) : 55 total : 57 table 5-1. functions of ports function name pin name dedicated input port input/output port. input/output specifiable bit-wise. when used as input port, on-chip pull-up resistor can be used in software . input/output port. input/output specifialbe bit-wise. when used as input port, on-chip pull-up resistor can be used in software . input/output port. input/output specifiable bit-wise. when used as input port, on-chip pull-up resistor can be used in software . input/output port. input/output specifiable bit-wise. when used as input port, on-chip pull-up resistor can be used in software. input/output port. input/output specifiable bit-wise. when used as input port, on-chip pull-up resistor can be used in software. input/output port. input/output specifiable bit-wise. when used as input port, on-chip pull-up resistor can be used in software. input/output port/segment signal output function specifiable in 2-bit units by lcd control register (lcdc). input/output port. input/output specifiable bit-wise. when used as input port, on-chip pull-up resistor can be used in software. input/output port/segment signal output function specifiable in 2-bit units by lcd control register (lcdc). input/output port. input/output specifiable bit-wise. when used as input port, on-chip pull-up resistor can be used in software. direct led drive capability. input/output port. input/output specifiable bit-wise. when used as input port, on-chip pull-up resistor can be used in software. test flag (krif) is set to 1 by falling edge detection. port 0 port 1 port 2 port 3 port 7 port 8 port 9 port 10 port 11 p00, p07 p01 to p05 p10 to p17 p25 to p27 p30 to p37 p70 to p72 p80 to p87 p90 to p97 p100 to p103 p110 to p117
20 m pd78062(a), 78063(a), 78064(a) interval timer 1 channel 2 channels 1 channel 1 channel external event counter 1 channel 2 channels C C timer output 1 output 2 outputs C C pwm output 1 output C C C pulse width measurement 2 inputs C C C square wave output 1 output 2 outputs C C one-shot pulse output 1 output C C C interrupt request 2 2 2 1 test input C C 1 input C 5.2 clock generator there are two kinds of clocks, main system clock and subsystem clock. the minimum instruction execution time can also be changed. 0.4 m s/0.8 m s/1.6 m s/3.2 m s/6.4 m s/12.8 m s (main system clock: in 5.0 mhz operation) 122 m s (subsystem clock: in 32.768 khz operation) figure 5-1. clock generator block diagram 5.3 timer/event counter five timer/event counter channels are incorporated. 16-bit timer/event counter : 1 channel 8-bit timer/event counter : 2 channels watch timer : 1 channel watchdog timer : 1 channel table 5-2. timer/event counter types and functions 16-bit timer/ event counter 8-bit timer/ event counter watch timer watchdog timer type function x1 x2 xt1/p07 xt2 f xt f xx 2 f xx 2 2 f xx 2 3 f xx 2 4 f xt 2 f x 2 stop f x cpu clock (f cpu ) subsystem clock oscillator main system clock oscillator scaler selec- tor prescaler prescaler standby control circuit selec- tor watch timer clock output function clock to peripheral hardware to intp0 sampling clock f xx 1/2
21 4 m pd78062(a), 78063(a), 78064(a) figure 5-2. 16-bit timer/event counter block diagram figure 5-3. 8-bit timer/event counter block diagram ti01/p01/intp1 watch timer output ti00/p00/intp0 2f xx f xx f xx /2 f xx /2 2 intp0 inttm01 intp1 inttm00 to0/p30 internal bus selec- tor 16-bit capture/compare register (cr00) match match pwm pulse output control circuit output control circuit edge detector 16-bit timer register (tm0) clear 16-bit capture/compare register (cr01) internal bus selec- tor selector inttm1 to2/p32 inttm2 to1/p31 f xx /2-f xx /2 9 f xx /2 11 ti1/p33 ti2/p34 f xx /2-f xx /2 9 f xx /2 11 internal bus 8-bit compare register (cr10) match match selec- tor 8-bit timer register 1 (tm1) clear selec- tor selector 8-bit compare register (cr20) 8-bit timer register 2 (tm2) clear selec- tor output control circuit output control circuit internal bus selec- tor
22 m pd78062(a), 78063(a), 78064(a) figure 5-4. watch timer block diagram figure 5-5. watchdog timer block diagram f w 2 4 f w 2 5 f w 2 6 f w 2 7 f w 2 8 f w 2 9 f xx /2 7 f xt f w f w 2 14 f w 2 13 intwt inttm3 selec- tor prescaler 5-bit counter selector selector selector to 16-bit timer/event counter to lcd controller/driver f xx 2 6 f xx 2 7 f xx 2 8 f xx 2 9 f xx 2 11 f xx 2 5 f xx 2 4 f xx 2 3 reset intwdt non-maskable interrupt request intwdt maskable interrupt request prescaler selector 8-bit counter control circuit
23 4 m pd78062(a), 78063(a), 78064(a) 5.4 clock output control circuit clocks of the following frequency can be output as clock outputs. 19.5 khz/39.1khz/78.1 khz/156 khz/313 khz/625 khz/1.25 mhz/2.5 mhz/5.0 mhz (main system clock: in 5.0 khz operation) 32.768 khz (subsystem clock: in 32.768 khz operation) figure 5-6. clock output circuit block diagram 5.5 buzzer output control circuit clocks of the following frequency can be output as buzzer outputs. 1.2 khz/2.4 khz/4.9 khz/9.8 khz (main system clock : in 5.0 mhz operation) figure 5-7. buzzer output control circuit block diagram pcl/p35 f xx /2 2 f xx /2 3 f xx /2 4 f xx /2 5 f xx /2 6 f xx /2 7 f xt selector synchronization circuit f xx /2 f xx output control circuit buz/p36 selector f xx /2 9 f xx /2 10 f xx /2 11 output control circuit
24 m pd78062(a), 78063(a), 78064(a) 5.6 a/d converter eight 8-bit resolution a/d converter channels are incorporated. the following two types of start-up method are available. hardware start software start figure 5-8. a/d converter block diagram 5.7 serial interface two clocked serial interface channels are incorporated. serial interface channel 0 serial interface channel 2 table 5-3. serial interface channel block diagram 3-wire serial i/o mode (msb/lsb-first switchable) (msb/lsb-first switchable) sbi (serial bus interface) mode (msb-first) 2-wire serial i/o mode (msb-first) asynchronous serial interface (dedicated baud rate generator (uart) mode incorpoorated) function serial interface channel 0 serial interface channel 2 ani0/p10 ani1/p11 ani2/p12 ani3/p13 ani4/p14 ani5/p15 ani6/p16 ani7/p17 av dd av ref av ss intad intp3 selec- tor sample & hold circuit intp3/p03 voltage comparator series resistor string tap selec- tor successive approximation register (sar) control circuit edge detector a/d conversion result register (adcr) internal bus
25 4 m pd78062(a), 78063(a), 78064(a) figure 5-9. serial interface channel 0 block diagram figure 5-10. serial interface channel 2 block diagram r x d/si2/p70 t x d/so2/p71 asck/sck2/p72 intser intsr/intcsi2 f xx -f xx /2 10 intst receive buffer register (rxb/sio2) direction control circuit receive shift register (rxs) direction control circuit transmit shift register (txs/sio2) transmit control circuit receive control circuit sck output control circuit baud rate generator internal bus si0/sb0/p25 so0/sb1/p26 sck0/p27 intcsi0 to2 f xx /2-f xx /2 8 internal bus selector selector serial i/o shift register 0 (sio0) output latch busy/acknowledge output circuit bus release/command/ acknowledge detector serial clock counter interrupt request signal generator serial clock control circuit selector
26 m pd78062(a), 78063(a), 78064(a) 5.8 lcd controller/driver an lcd controller/driver with the following functions is incorporated. selection of 5 types of display mode 16 of the segment signal of outputs can be switched to input/output ports in units of 2. (p80/s39 to p87/s32, p90/s31 to p97/s24) table 5-4. display mode types and maximum number of display pixels bias method time multiplexing common signal used maximum number of display pixels static com0 (com1 to com3) 40 (40 segments 1 common) 2 com0, com1 80 (40 segments 2 commons) 3 com0 to com2 3 com0 to com2 4 com0 to com3 160 (40 segments 4 commons) 1/2 1/3 120 (40 segments 3 commons) figure 5-11. lcd controller/driver block diagram v lc2 v lc1 v lc0 bias com3 com2 com1 com0 s39/p80 s0 s23 s24/p97 lcdcl f w 2 9 f w 2 8 f w 2 7 f w 2 6 internal bus display data memory segment data selector port output data segment driver prescaler selector timing controller lcd drive voltage generator common driver
27 m pd78062(a), 78063(a), 78064(a) 6. interrupt functions and test functions 6.1 interrupt functions the following three types, 20 sources of interrupt functions are available: non-maskable : 1 maskable : 18 software : 1
28 m pd78062(a), 78063(a), 78064(a) table 6-1. interrupt source list interrupt source name interrupt type default priority note1 internal/ external vector table address basic con- figuration type note2 watchdog timer overflow (with watchdog timer mode 1 selected) watchdog timer overflow (with interval timer mode selected) pin input edge detection serial interface channel 0 transfer termination serial interface channel 2 uart reception error generation serial interface channel 2 uart reception termination serial interface channel 2 3-wire transfer termination serial interface channel 2 uart transmission termination reference time interval signal from watch timer 16-bit timer register and capture/compare register (cr00) match signal generation 16-bit timer register and capture/compare register (cr01) match signal generation 8-bit timer/event counter 1 match signal generation 8-bit timer/event counter 2 match signal generation a/d converter conversion termination brk instruction execution intwdt intwdt intp0 intp1 intp2 intp3 intp4 intp5 intcsi0 intser intsr intcsi2 intst inttm3 inttm00 inttm01 inttm1 inttm2 intad brk trigger (a) (b) internal 0004h 0006h 0008h 000ah 000ch 000eh 0010h 0014h 0018h 001ah 001ch 001eh 0020h 0022h 0024h 0026h 0028h 003eh (c) (d) external internal (b) (e) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 0 maskable software notes 1. default priority is a priority order when more than one maskable interrupt request is generated simultaneously. 0 is the highest and 16 the lowest. 2. basic configuration types (a) to (e) correspond to those shown in figure 6-1. non- maskable
29 m pd78062(a), 78063(a), 78064(a) figure 6-1. basic configuration of interrupt functions (1/2) (a) internal non-maskable interrupt interrupt request standby release signal internal bus vector table address generator priority control circuit (b) intrnal maskable interrupt mk ie pr isp if interrupt request internal bus priority control circuit vector table address generator standby release signal (c) external maskable interrupt (intp0) sampling clock select register (scs) if ie pr isp external interrupt mode register (intm0) sampling clock edge detector interrupt request internal bus mk priority control circuit vector table address generator standby release signal
30 m pd78062(a), 78063(a), 78064(a) figure 6-1. basic configuration of interrupt functions (2/2) (d) external maskable interrupt (except intp0) if internal bus interrupt request edge detector vector table address generator standby release signal external interrupt mode register (intm0, intm1) mk ie pr isp priority control circuit (e) software interrupt internal bus interrupt request vector table address generator priority control circuit if : interrupt request flag ie : interrupt enable flag isp : in-service priority flag mk : interrupt mask flag pr : priority specification flag
31 m pd78062(a), 78063(a), 78064(a) 6.2 test functions there are two sources of test functions as shown in table 6-2. table 6-2. test input source list figure 6-2. basic configuration of test function if : test input flag mk : test mask flag test input source name trigger internal/external intwt watch timer overflow internal intpt11 port 11 falling edge detection external mk if internal bus standby release signal test input signal
32 m pd78062(a), 78063(a), 78064(a) 7. standby function the standby function is a function to reduce the consumption current and there are the following two kinds of standby functions. l halt mode : halts cpu operating clock and can reduce average consumption current by the intermittent operation along with the normal operation. l stop mode : halts main system clock oscillation. halts all operations with the main system clock and sets ultra-low consumption current state with subsystem clock only. figure 7-1. standby function note halting the main system clock enables the consumption current to be reduced. when the cpu is operated by the subsystem clock, the main system clock should be halted by setting the bit 7 (mcc) of the processor clock control register (pcc). the stop instruction is not available. caution when the main system clock is stopped and the system is operated by the subsystem clock, the main system clock should be returned to after securing the oscillation stabilization time in software. 8. reset function there are the following two kinds of resetting methods. external reset by reset pin. internal reset by watchdog timer hung-up time detection. css=1 css=0 main system clock operation interrupt request stop mode main system clock oscillation halted stop instruction () interrupt request halt instruction halt mode clock supply to cpu halted, oscillation maintained () subsystem clock operation note halt instruction interrupt request halt mode note clock supply to cpu halted, oscillation maintained ()
33 m pd78062(a), 78063(a), 78064(a) 9. instruction set (1) 8-bit instruction mov, xch, add, addc, sub, subs, and, or, xor, cmp, mulu, divuw, inc, dec, ror, rol, rorc, rolc, ror4, rol4, push, pop, dbnz #byte a r note sfr saddr !addr16 psw [de] [hl] $addr16 1 none 2nd operand 1st operand add addc sub subc and or xor cmp mov mov mov add addc sub subc and or xor cmp mov mov add addc sub subc and or xor cmp mov mov mov mov mov mov mov mov xch mov xch add addc sub subc and or xor cmp mov xch add addc sub subc and or xor cmp mov xch add addc sub subc and or xor cmp mov mov xch mov xch add addc sub subc and or xor cmp mov xch add addc sub subc and or xor cmp [hl+byte] [hl+b] [hl+c] ror rol rorc rolc inc dec inc dec push pop ror4 rol4 mulu divuw dbnz dbnz a r b, c sfr saddr !addr16 psw [de] [hl] [hl+byte] [hl+b] [hl+c] x c note except r = a
34 m pd78062(a), 78063(a), 78064(a) 2nd operand 1st operand #word ax rp note sfrp saddrp !addr16 sp none a rp sfrp saddrp !addr16 sp addw subw cmpw movw movw movw movw movw note movw movw movw movw movw movw movw movw incw, decw push, pop movw xchw note only when rp=bc, de, hl (3) bit manipulation instruction mov1, and1, or1, xor1, set1, clr1, not1, bt, bf, btclr 2nd operand 1st operand a.bit sfr.bit saddr.bit psw.bits [hl].bit cy $addr16 none a.bit sfr.bit saddr.bit psw.bit [hl].bit cy mov1 and1 or1 xor1 mov1 and1 or1 xor1 mov1 and1 or1 xor1 mov1 and1 or1 xor1 bt, bf, btclr dbnz callt callf call br br basic instruction compound instruction (5) other instructions adjba, adjbs, brk, ret, reti, retb, sel, nop, ei, di, halt, stop (2) 16-bit instruction movw, xchw, addw, subw, cmpw, push, pop, incw, decw (4) call instruction/branch instruction call, callf, callt, br, bc, bnc, bz, bnz, bt, bf, btclr, dnzb br, bc, bnc, bz, bnz 2nd operand 1st operand ax !addr16 !addr11 [addr5] $addr16 mov1 mov1 mov1 mov1 mov1 set1 clr1 set1 clr1 set1 clr1 set1 clr1 set1 clr1 set1 clr1 not1 bt bf btclr bt bf btclr bt bf btclr bt bf btclr bt bf btclr mov1 and1 or1 xor1
35 m pd78062(a), 78063(a), 78064(a) 10. electrical specifications absolute maximum ratings (t a = 25 c) v dd av dd av ref av ss v i v o v an i oh i ol note parameter symbol test conditions rating unit p10 to p17 analog input pin 1 pin total for p00 to p05, p07, p10 to p17, p100, p101 & p110 to p117 total for p25 to p27, p30 to p37, p70 to p72, p80 to p87, p90 to p97, p102 & p103 C0.3 to +7.0 C0.3 to v dd + 0.3 C0.3 to v dd + 0.3 C0.3 to +0.3 C0.3 to v dd + 0.3 C0.3 to v dd + 0.3 av ss C 0.3 to av ref + 0.3 C10 C15 C15 30 15 100 70 100 70 50 20 C40 to +85 C65 to +150 v v v v v v v ma ma ma ma ma ma ma ma ma ma ma c c peak value rms value peak value rms value peak value rms value peak value rms value 1 pin total for p00 to p05, p10 to p17, p100, p101 & p110 to p117 total for p30 to p37, p102 & p103 total for p25 to p27, p70 to p72, p80 to p87 & p90 to p97 supply voltage input voltage output voltage analog input voltage output current high output current low t a t stg operating ambient temperature storage temperature note the rms value should be calculated as follows: [rms value] = [peak value] duty caution the product quality may be damaged even if a value of only one of the above parameters exceeds the absolute maximum rating or any value exceeds the absolute maximum rating for an instant. that is, the absolute maximum rating is a rating value which may cause a product to be damaged physically. the absolute maximum rating values must therefore be observed in using the product. remark unless otherwise specified, the characteristics of dual-function pins are the same as those of port pins. ?
36 m m pd78062(a), 78063(a), 78064(a) permissible inrush current characteristics of pins on application of overvoltage (t a = C40 to +85 c, v dd = 2.0 to 6.0 v) parameter symbol conditions min. typ. max. unit positive inrush current i ijh1 1 pin input ports other than peak value 5.00 ma (v in > v dd ) anin (n = 0 to 7) mean value 0.50 ma i ijh2 anin (n = 0 to 7) note 1 peak value 1.50 ma mean value 0.15 ma i ijh3 total of input ports other than peak value 40.0 ma all input anin (n = 0 to 7) mean value 4.00 ma i ijh4 pins anin (n = 0 to 7) note 2 peak value 1.50 ma mean value 0.15 ma negative inrush current i ijl1 1 pin input ports other than peak value C0.50 ma (v in < v ss ) anin (n = 0 to 7) mean value C0.05 ma i ijl2 anin (n = 0 to 7) note 1 peak value C0.50 ma mean value C0.05 ma i ijl3 total of input ports other than peak value C4.00 ma all input anin (n = 0 to 7) mean value C0.40 ma i ijl4 pins anin (n = 0 to 7) note 2 peak value C1.50 ma mean value C0.15 ma notes 1. if an inrush current flows to one analog input pin (anin: n = 0 to 7), the a/d conversion result of the analog input pin is the value when the inrush current does not flow 2 lsb. 2. if an inrush current flows to two or more analog input pins (anin: n = 0 to 7), the a/d conversion result of the analog input pin is the value when the inrush current does not flow 4 lsb. remarks 1. the mean value (absolute value) of the inrush current of a pin can be calculated by the following expression: mean value = ((1/t) t 0 | i (t) | 3/2 dt) 2/3 where i (t) is a pin inrush current, and the maximum value of |i (t)| is the peak value. 2. v in is the input voltage applied to the pin. capacitance (t a = 25 c, v dd = v ss = 0 v) input capacitance output capacitance i/o capacitance pf pf pf 15 15 15 c in c out c io f = 1 mhz unmeasured pins returned to 0 v. parameter symbol test conditions min. typ. max. unit
37 m pd78062(a), 78063(a), 78064(a) main system clock oscillator characteristics (t a = C40 to +85 c, v dd = 2.0 to 6.0 v) unit mhz ms mhz ms mhz ns max. 5 4 5 10 30 5.0 500 recommended circuit parameter oscillator frequency (f x ) note1 oscillation stabilization time note2 oscillator frequency (f x ) note1 oscillation stabilization time note2 x1 input frequency (f x ) note1 x1 input high/low level width (t xh , t xl ) min. 1 1 1.0 85 oscillator ceramic oscillator crystal resonator external clock notes 1. indicates only oscillator characteristics. refer to ac characteristics for instruction execution time. 2. time required to stabilize oscillation after reset or stop mode release. cautions 1. when using the main system clock oscillator, wiring in the area enclosed with the dotted line should be carried out as follows to avoid an adverse effect from wiring capacitance. ? wiring should be as short as possible. ? wiring should not cross other signal lines. ? wiring should not be placed close to a varying high current. ? the potential of the oscillator capacitor ground should be the same as v ss . ? do not ground it to the ground pattern in which a high current flows. ? do not fetch a signal from the oscillator. 2. if the main system clock oscillator is operated by the subsystem clock when the main system clock is stopped, reswitching to the main system clock should be performed after the stable oscillation time has been obtained by the program. typ. x1 x2 m pd74hcu04 test conditions v dd = oscillator voltage range after v dd reaches oscil- lator voltage range min. v dd = 4.5 to 6.0 v x1 x2 ic c1 c2 x1 x2 ic c1 c2
38 m m pd78062(a), 78063(a), 78064(a) subsystem clock oscillator characteristics (t a = C40 to +85 c, v dd = 2.0 to 6.0 v) v dd = 4.5 to 6.0 v crystal resonator external clock oscillator frequency (f xt ) note1 oscillation stabilization time note2 xt1 input frequency (f xt ) note1 xt1 input high-/low-level width (t xth /t xtl ) 35 2 10 100 15 32.768 1.2 32 32 5 xt1 xt2 resonator recommended circuit parameter test conditions min. typ. max. unit r2 xt2 xt1 ic c4 c3 khz s khz m s notes 1. indicates only oscillator characteristics. refer to ac characteristics for instruction execution time. 2. time required to stabilize oscillation after v dd has reached the minimum oscillation voltage range. cautions 1. when using the subsystem clock oscillator, wiring in the area enclosed with the dotted line should be carried out as follows to avoid an adverse effect from wiring capacitance. ? wiring should be as short as possible. ? wiring should not cross other signal lines. ? wiring should not be placed close to a varying high current. ? the potential of the oscillator capacitor ground should be the same as v ss . ? do not ground it to the ground pattern in which a high current flows. ? do not fetch a signal from the oscillator. 2. the subsystem clock oscillator is designed as a low amplification circuit to provide low consumption current, causing misoperation by noise more frequently than the main system clock oscillation circuit. special care should therefore be taken to wiring method when the subsystem clock is used.
39 m pd78062(a), 78063(a), 78064(a) c3 (pf) c4 (pf) r2 (k w ) min. (v) max. (v) 32.768 15 22 220 2.0 6.0 c1 (pf) c2 (pf) min. (v) max. (v) csa5.00mg 5.00 30 30 2.2 6.0 cst5.00mgw 5.00 built-in built-in 2.7 6.0 ef0gc5004a4 5.00 built-in built-in 2.7 6.0 lead type ef0ec5004a4 5.00 built-in built-in 2.0 6.0 round lead type ef0en5004a4 5.00 33 33 2.7 6.0 lead type ef0s5004b5 5.00 built-in built-in 2.7 6.0 chip type kbr-5.0msa 5.00 33 33 2.7 6.0 lead type pbrc5.00a 5.00 33 33 2.7 6.0 chip type kbr-5.0mks 5.00 built-in built-in 2.7 6.0 lead type kbr-5.0mws 5.00 built-in built-in 2.7 6.0 chip type main system clock: ceramic oscillator (t a = C40 to +85 c) murata mfg. co., ltd. recommended oscillator constant product name matsushita electronics components co., ltd. kyocera corporation oscillator voltage range recommended circuit constant manufacturer remarks subsystem clock: crystal resonator (t a = C40 to +60 c) product name manufacturer oscillator voltage range recommended circuit constant kyocera corporation kf-38g-12p0200 note (load capacitance 12 pf) frequency (mhz) frequency (khz) note kf-38g-12p0200 is a maintenance product. caution the oscillation circuit constants and oscillation voltage range indicate conditions for stable oscillation. however, they do not guarantee accuracy of the oscillation frequency. if the application circuit requires accuracy of the oscillation frequency, it is necessary to set the oscillation frequency in the application circuit. for this, it is necessary to directly contact the manufacturer of the resonator being used.
40 m m pd78062(a), 78063(a), 78064(a) dc characteristics (t a = C40 to +85 c, v dd = 2.0 to 6.0 v) 0.7 v dd v dd v 0.8 v dd v dd v 0.8 v dd v dd v 0.85 v dd v dd v v dd C0.5 v dd v v dd C0.2 v dd v 0.8 v dd v dd v 0.9 v dd v dd v 0.9 v dd v dd v 0 0.3 v dd v 0 0.2 v dd v 0 0.2 v dd v 0 0.15 v dd v 0 0.4 v 0 0.2 v 0 0.2 v dd v 0 0.1 v dd v 0 0.1 v dd v v dd C1.0 v dd v v dd C0.5 v dd v 0.4 2.0 v 0.4 v 0.2 v dd v 0.5 v p10 to p17, p30 to p32, p35 to p37, p80 to p87, p90 to p97, p100 to p103 p00 to p05, p25 to p27, p33, p34, p70 to p72, p110 to p117, reset x1, x2 xt1/p07, xt2 p10 to p17, p30 to p32, p35 to p37, p80 to p87, p90 to p97, p100 to p103 p00 to p05, p25 to p27, p33, p34, p70 to p72, p110 to p117, reset x1, x2 xt1/p07, xt2 v dd = 4.5 to 6.0 v, i oh = C1 ma i oh = C100 m a p100 to p103 p00 to p05, p10 to p17, p25 to p27, p30 to p37, p70 to p72, p80 to p87, p90 to p97, p110 to p117 sb0, sb1, sck0 i ol = 400 m a output voltage high v dd = 4.5 to 6.0 v, i ol = 15 ma v dd = 4.5 to 6.0 v, i ol = 1.6 ma 4.5 v v dd 6.0 v, open-drain, pulled high (r = 1 k w ) output voltage low note when p07/xt1 is used as p07, the inverse phase of p07 should be input to xt2. remark unless otherwise specified, the characteristics of dual-function pins are the same as those of port pins. v ih1 v ih2 v ih3 v ih4 v il1 v il2 v il3 v il4 v oh v ol1 v ol2 v ol3 input voltage high input voltage low v dd = 2.7 to 6.0 v v dd = 2.7 to 6.0 v v dd = 2.7 to 6.0 v 4.5 v v dd 6.0 v 2.7 v v dd < 4.5 v 2.0 v v dd < 2.7 v note v dd = 2.7 to 6.0 v v dd = 2.7 to 6.0 v v dd = 2.7 to 6.0 v 4.5 v v dd 6.0 v 2.7 v v dd < 4.5 v 2.0 v v dd < 2.7 v note parameter symbol test conditions min. typ. max. unit
41 m pd78062(a), 78063(a), 78064(a) symbol test conditions min. typ. max. unit p00 to p05, p10 to p17, p25 to p27, p30 to p37, p70 to p72, p80 to p87, 3 m a p90 to p97, p100 to p103, p110 to p117 i lih2 x1, x2, xt1/p07, xt2 20 m a p00 to p05, p10 to p17, p25 to p27, p30 to p37, p70 to p72, p80 to p87, C3 m a p90 to p97, p100 to p103, p110 to p117 i lil2 x1, x2, xt1/p07, xt2 C20 m a i loh v o = v dd 3 m a i lol v o = 0 v C3 m a v i = 0 v, p01 to p05, p10 to p17, p25 to p27, r p30 to p37, p70 to p72, p80 to p87, p90 to p97, p100 to p103, p110 to p117 v dd = 5.0 v 10 % note4 412ma v dd = 3.0 v 10 % note5 0.6 1.8 ma v dd = 2.2 v 10 % note5 0.35 1.05 ma v dd = 5.0 v 10 % note4 6.5 19.5 ma v dd = 3.0 v 10 % note5 0.8 2.4 ma v dd = 5.0 v 10 % 1.4 4.2 ma v dd = 3.0 v 10 % 500 1500 m a v dd = 2.2 v 10 % 280 840 m a v dd = 5.0 v 10 % 1.6 4.8 ma v dd = 3.0 v 10 % 650 1950 m a dc characteristics (t a = C40 to +85 c, v dd = 2.0 to 6.0 v) parameter v i = v dd i lih1 v i = 0 v i lil1 i dd2 2.7 v v dd < 4.5 v 20 500 k w input leakage current high input leakage current low output leakage current high output leakage current low software pull-up resistor supply current note1 4.5 v v dd 6.0 v 15 40 90 k w remark unless otherwise specified, the characteristics of dual-function pins are the same as those of port pins. notes 1. not including currents flowing in on-chip pull-up resistors or lcd split resistors. 2. main system clock f xx = f x /2 operation (when oscillation mode selection register (osms) is set to 00h) 3. main system clock f xx = f x operation (when osms is set to 01h) 4. high-speed mode operation (when processor clock control register (pcc) is set to 00h) 5. low-speed mode operation (when pcc is set to 04h) 5.00 mhz, crystal oscillation (f xx = 2.5 mhz) note2 operating mode i dd1 5.00 mhz, crystal oscillation (f xx = 5.0 mhz) note3 halt mode 5.00 mhz, crystal oscillation (f xx = 2.5 mhz) note2 halt mode 5.00 mhz, crystal oscillation (f xx = 5.0 mhz) note3 operating mode
42 m m pd78062(a), 78063(a), 78064(a) parameter dc characteristics (t a = C40 to +85 c, v dd = 2.0 to 6.0 v) symbol test conditions min. typ. max. unit v dd = 5.0 v 10 % 60 120 m a v dd = 3.0 v 10 % 32 64 m a v dd = 2.2 v 10 % 24 48 m a v dd = 5.0 v 10 % 25 55 m a v dd = 3.0 v 10 % 5 15 m a v dd = 2.2 v 10 % 2.5 12.5 m a v dd = 5.0 v 10 % 1 30 m a v dd = 3.0 v 10 % 0.5 10 m a v dd = 2.2 v 10 % 0.3 10 m a v dd = 5.0 v 10 % 0.1 30 m a v dd = 3.0 v 10 % 0.05 10 m a v dd = 2.2 v 10 % 0.05 10 m a notes 1. not including currents flowing in on-chip pull-up resistors or lcd split resistors. 2. when the main system clock is stopped. xt1 = v dd stop mode when feedback resistor is connected 32,768 khz, crystal oscillation operating mode note2 i dd3 32,768 khz, crystal oscillation halt mode note2 xt1 = v dd stop mode when feedback resistor is disconnected i dd6 i dd5 supply current note1 i dd4
43 m pd78062(a), 78063(a), 78064(a) symbol test conditions min. typ. max. unit lcd drive voltage v lcd 2.5 v dd v lcd split resistor r lcd 60 100 150 k w lcd output voltage deviation note (common) lcd output voltage deviation note (segment) dc characteristics (t a = C10 to +85 c) symbol test conditions min. typ. max. unit lcd drive voltage v lcd 2.0 v dd v lcd split resistor r lcd 60 100 150 k w lcd output voltage deviation note (common) lcd output voltage deviation note (segment) parameter (1) static display mode (v dd = 2.0 to 6.0 v) v odc i o = 5 m a0 0.2 v v ods i o = 1 m a0 0.2 v 2.0 v v lcd v dd v lcd0 = v lcd note the voltage deviation is the difference from the output voltage corresponding to the ideal value of the segment and common outputs (v lcdn ; n = 0, 1, 2). parameter (2) 1/3 bias method (v dd = 2.5 to 6.0 v) note the voltage deviation is the difference from the output voltage corresponding to the ideal value of the segment and common outputs (v lcdn ; n = 0, 1, 2). symbol test conditions min. typ. max. unit lcd drive voltage v lcd 2.7 v dd v lcd split resistor r lcd 60 100 150 k w lcd output voltage deviation note (common) lcd output voltage deviation note (segment) (3) 1/2 bias method (v dd = 2.7 to 6.0 v) note the voltage deviation is the difference from the output voltage corresponding to the ideal value of the segment and common outputs (v lcdn ; n = 0, 1, 2). v odc i o = 5 m a0 0.2 v v ods i o = 1 m a0 0.2 v 2.7 v v lcd v dd v lcd0 = v lcd v lcd1 = v lcd 1/2 v lcd2 = v lcd1 v odc i o = 5 m a0 0.2 v v ods i o = 1 m a0 0.2 v 2.5 v v lcd v dd v lcd0 = v lcd v lcd1 = v lcd 2/3 v lcd2 = v lcd 1/3 parameter
44 m m pd78062(a), 78063(a), 78064(a) ac characteristics (1) basic operation (t a = C40 to +85 c, v dd = 2.0 to 6.0 v) parameter t cy f ti1 t tih1, t til1 t inth , t intl t rsl notes 1. main system clock f xx = f x /2 operation (when oscillation mode selection register (osms) is set to 00h) 2. main system clock f xx = f x operation (when osms is set to 01h) 3. this is the value when the external clock is used. the value is 114 m s (min.) when the crystal resonator is used. 4. in combination with bits 0 (scs0) and 1 (scs1) of sampling clock select register (scs), selection of f sam is possible between f xx /2 n , f xx /32, f xx /64 and f xx /128 (when n = 0 to 4). cycle time (minimum instruction execution time) ti00 input frequency ti00 input high/ low-level width ti01 input high/ low-level width ti1, ti2 input high/ low-level width ti1, ti2 input high/ low-level width interrupt input high/low-level width reset low level width symbol test conditions min. typ. max. unit operating on main system clock v dd = 2.7 to 6.0 v 0.8 64 m s (f xx = 2.5 mhz) note1 2.2 64 m s operating on main system clock 4.5 v dd 6.0 v 0.4 32 m s (f xx = 5.0 mhz) note2 2.7 v dd < 4.5 v 0.8 32 m s operating on subsystem clock 40 note3 122 125 m s t ti00 = t tih00 + t til00 0 1/t ti00 mhz 4.5 v v dd 6.0 v 2/f sam +0.1 note 4 m s 2.7 v v dd < 4.5 v 2/f sam +0.2 note 4 m s 2.0 v v dd < 2.7 v 2/f sam +0.5 note 4 m s 2.7 v v dd 6.0 v 10 m s 20 m s v dd = 4.5 to 6.0 v 0 4 mhz 0 275 khz v dd = 4.5 to 6.0 v 100 ns 1.8 m s intp0 8/f sam note4 m s intp1 to intp5, v dd = 2.7 to 6.0 v 10 m s p110 to p117 20 m s v dd = 2.7 to 6.0 v 10 m s 20 m s f ti00 f tih00, t til00 f tih01, t til01
45 m pd78062(a), 78063(a), 78064(a) t cy vs v dd (at main system clock f xx = f x /2 operation) t cy vs v dd (at main system clock f xx = f x operation) 60 10 2.0 1.0 1 023456 0.8 0.4 60 10 2.0 1.0 1 023456 0.8 0.4 supply voltage v dd [v] cycle time t cy [ s] m guaranteed operation range supply voltage v dd [v] cycle time t cy [ s] m guaranteed operation range 32
46 m m pd78062(a), 78063(a), 78064(a) (2) serial interface (t a = C40 to +85 c, v dd = 2.0 to 6.0 v) (a) serial interface channel 0 (i) 3-wire serial i/o mode (sck0... internal clock output) sck0 cycle time sck0 high/low-level width si0 setup time (to sck0 - ) si0 hold time (from sck0 - ) so0 output delay time from sck0 note c is the load capacitance of sck0, so0 output line. (ii) 3-wire serial i/o mode (sck0...external clock input) sck0 cycle time sck0 high/low-level width si0 setup time (to sck0 - ) si0 hold time (from sck0 - ) so0 output delay time from sck0 sck0 rise, fall time t kh2 , t kl2 note c is the load capacitance of so0 output line. parameter symbol test conditions min. typ. max. unit 4.5 v v dd 6.0 v 800 ns t kcy2 2.7 v v dd < 4.5 v 1600 ns 3200 ns 4.5 v v dd 6.0 v 400 ns 2.7 v v dd < 4.5 v 800 ns 1600 ns t sik2 100 ns t ksi2 400 ns t kso2 c = 100 pf note 300 ns 1000 ns parameter symbol test conditions min. typ. max. unit 4.5 v v dd 6.0 v 800 ns t kcy1 2.7 v v dd < 4.5 v 1600 ns 3200 ns t kh1 ,v dd = 4.5 to 6.0 v t kcy1 /2C50 ns t kl1 t kcy1 /2C100 ns 4.5 v v dd 6.0 v 100 ns t sik1 2.7 v v dd < 4.5 v 150 ns 300 ns t ksi1 400 ns t kso1 c = 100 pf note 300 ns t r2 , t f2
47 m pd78062(a), 78063(a), 78064(a) (iii) sbi mode (sck0...internal clock output) parameter symbol test conditions min. typ. max. unit v dd = 4.5 to 6.0 v 800 ns 3200 ns v dd = 4.5 to 6.0 v t kcy3 /2C50 ns t kcy3 /2C150 ns v dd = 4.5 to 6.0 v 100 ns 300 ns r = 1 k w ,v dd = 4.5 to 6.0 v 0 250 ns c = 100 pf note 0 1000 ns t kcy3 ns t kcy3 ns t kcy3 ns t kcy3 ns sck0 cycle time sck0 high/low-level width sb0, sb1 setup time (to sck0 - ) sb0, sb1 hold time (from sck0 - ) sb0, sb1 output delay time from sck0 sb0, sb1 from sck0 - sck0 from sb0, sb1 sb0, sb1 high-level width sb0, sb1 low-level width t kcy3 t kh3 , t kl3 t sik3 t ksi3 t kso3 t ksb t sbk t sbh t sbl t kcy3 /2 ns note r and c are the load resistance and load capacitance of the sck0, sb0 and sb1 output line. (iv) sbi mode (sck0...external clock input) parameter symbol test conditions min. typ. max. unit v dd = 4.5 to 6.0 v 800 ns 3200 ns v dd = 4.5 to 6.0 v 400 ns 1600 ns v dd = 4.5 to 6.0 v 100 ns 300 ns r = 1 k w ,v dd = 4.5 to 6.0 v 0 300 ns c = 100 pf note 0 1000 ns t kcy4 ns t kcy4 ns t kcy4 ns t kcy4 ns 1000 ns t kcy4 /2 ns note r and c are the load resistance and load capacitance of the sb0 and sb1 output line. t kcy4 t kh4 , t kl4 t sik4 t ksi4 t kso4 t ksb t sbk t sbh t sbl t r4 , t f4 sck0 cycle time sck0 high/low-level width sb0, sb1 setup time (to sck0 - ) sb0, sb1 hold time (from sck0 - ) sb0, sb1 output delay time from sck0 sb0, sb1 from sck0 - sck0 from sb0, sb1 sb0, sb1 high-level width sb0, sb1 low-level width sck0 rise, fall time
48 m m pd78062(a), 78063(a), 78064(a) (v) 2-wire serial i/o mode (sck0... internal clock output) parameter symbol test conditions min. typ. max. unit v dd = 2.7 to 6.0 v 1600 ns 3200 ns v dd = 2.7 to 6.0 v t kcy5 /2C160 ns t kcy5 /2C190 ns v dd = 4.5 to 6.0 v t kcy5 /2C50 ns t kcy5 /2C100 ns 4.5 v v dd 6.0 v 300 ns 2.7 v v dd < 4.5 v 350 ns 400 ns 600 ns 300 ns t kcy5 t ksi5 t kso5 t sik5 t kh5 t kl5 r = 1 k w , c = 100 pf note t kcy6 t kh6 t kl6 t sik6 t ksi6 t kso6 (vi) 2-wire serial i/o mode (sck0... external clock input) sck0 cycle time sck0 high-level width sck0 low-level width sb0, sb1 setup time (to sck0 - ) sb0, sb1 hold time (from sck0 - ) sb0, sb1 output delay time from sck0 note r and c are the load resistance and load capacitance of the sck0, sb0 and sb1 output line. note r and c are the load resistance and load capacitance of the sb0 and sb1 output line. parameter symbol test conditions min. typ. max. unit v dd = 2.7 to 6.0 v 1600 ns 3200 ns v dd = 2.7 to 6.0 v 650 ns 1300 ns v dd = 2.7 to 6.0 v 800 ns 1600 ns 100 ns t kcy6 /2 ns r = 1 k w ,v dd = 4.5 to 6.0 v 0 300 ns c = 100 pf note 0 500 ns 1000 ns sck0 cycle time sck0 high-level width sck0 low-level width sb0, sb1 setup time (to sck0 - ) sb0, sb1 hold time (from sck0 - ) sb0, sb1 output delay time from sck0 sck0 rise, fall time t r6 , t f6
49 m pd78062(a), 78063(a), 78064(a) (b) serial interface channel 2 (i) 3-wire serial i/o mode (sck2... internal clock output) sck2 cycle time sck2 high/low-level width si2 setup time (to sck2 - ) si2 hold time (from sck2 - ) so2 output delay time from sck2 note c is the load capacitance of sck2, so2 output line. (ii) 3-wire serial i/o mode (sck2...external clock input) sck2 cycle time sck2 high/low-level width si2 setup time (to sck2 - ) si2 hold time (from sck2 - ) so2 output delay time from sck2 sck2 rise, fall time note c is the load capacitance of so2 output line. parameter symbol test conditions min. typ. max. unit 4.5 v v dd 6.0 v 800 ns t kcy8 2.7 v v dd < 4.5 v 1600 ns 3200 ns 4.5 v v dd 6.0 v 400 ns 2.7 v v dd < 4.5 v 800 ns 1600 ns t sik8 100 ns t ksi8 400 ns t kso8 c = 100 pf note 300 ns 1000 ns parameter symbol test conditions min. typ. max. unit 4.5 v v dd 6.0 v 800 ns t kcy7 2.7 v v dd < 4.5 v 1600 ns 3200 ns t kh7 ,v dd = 4.5 to 6.0 v t kcy1 /2C50 ns t kl7 t kcy1 /2C100 ns 4.5 v v dd 6.0 v 100 ns t sik7 2.7 v v dd < 4.5 v 150 ns 300 ns t ksi7 400 ns t kso7 c = 100 pf note 300 ns t r8 , t f8 t kh8 , t kl8
50 m m pd78062(a), 78063(a), 78064(a) parameter symbol test conditions min. typ. max. unit 4.5 v v dd 6.0 v 800 ns t kcy9 2.7 v v dd < 4.5 v 1600 ns 3200 ns 4.5 v v dd 6.0 v 400 ns 2.7 v v dd < 4.5 v 800 ns 1600 ns 4.5 v v dd 6.0 v 39063 bps 2.7 v v dd < 4.5 v 19531 bps 9766 bps 1000 ns parameter symbol test conditions min. typ. max. unit 4.5 v v dd 6.0 v 78125 bps 2.7 v v dd < 4.5 v 39063 bps 19531 bps transfer rate (iii) uart mode (dedicated baud rate generator output) t kh9 , t kl9 asck cycle time asck high/low-level width transfer rate asck rise, fall time (iv) uart mode (external clock input) t r9 , t f9
51 m pd78062(a), 78063(a), 78064(a) ac timing test point (excluding x1, xt1 input) clock timing ti timing 0.8 v dd 0.2 v dd 0.8 v dd 0.2 v dd test points t xl t xh 1/f x v ih3 (min.) v il3 (max.) t xtl t xth 1/f xt v ih4 (min.) v il4 (max.) x1 input xt1 input t til1 t tih1 1/f ti1 ti0?i2 t til00, t til01 t tih00, t tih01 ti00, ti01
52 m m pd78062(a), 78063(a), 78064(a) serial transfer timing 3-wire serial i/o mode: sbi mode (bus release signal transfer): sbi mode (command signal transfer): t kcy 1, 2, 7, 8 t kl1, 2, 7, 8 t kh1, 2, 7, 8 sck0, sck2 si0, si2 so0, so2 t sik1, 2, 7, 8 t ksi1, 2, 7, 8 t kso1, 2, 7, 8 input data output data t r2, 8 t f2, 8 t sik3, 4 t kcy3, 4 t kl3, 4 t kh3, 4 sck0 t sbl t sbh t ksb t sbk t ksi3, 4 t kso3, 4 sb0, sb1 t r4 t f4 t sik3, 4 t kcy3, 4 t kl3, 4 t kh3, 4 sck0 t ksb t sbk t ksi3.4 t kso3, 4 sb0, sb1 t r4 t f4
53 m pd78062(a), 78063(a), 78064(a) 2-wire serial i/o mode: uart mode: a/d converter (t a = C40 to +85 c, av dd = v dd = 2.0 to 6.0 v, av ss = v ss = 0 v) parameter symbol test conditions min. typ. max. unit 8 8 8 bit 2.7 v av ref 6.0 v 0.6 % 1.4 % t conv 19.1 200 m s t samp 12/f xx m s v ian av ss av ref v av ref 2.0 av dd v r airef 414 k w resolution overall error note conversion time sampling time analog input voltage reference voltage av ref -av ss resistance note quantization error ( 1/2 lsb) is not included. this is expressed in proportion to the full-scale value. t kso5, 6 t sik5, 6 t kcy5.6 t kl5, 6 t kh5, 6 sck0 t ksi5, 6 sb0, sb1 t r6 t f6 asck t kcy9 t kl9 t kh9 t r9 t f9
54 m m pd78062(a), 78063(a), 78064(a) data retention supply voltage v dddr = 1.8 v i dddr subsystem clock stopped and 0.1 10 m a feed-back resistor disconnected release signal set time t srel 0 m s oscillation release by reset 2 17 /f x ms stabilization t wait wait time release by interrupt note ms data memory stop mode low supply voltage data retention characteristics (t a = C40 to +85 c) parameter symbol test conditions min. typ. max. unit v dddr 1.8 6.0 v note in combination with bits 0 to 2 (osts0 to osts2) of oscillation stabilization time select register (osts), selection of 2 12 /f xx and 2 14 /f xx to 2 17 /f xx is possible. data retention timing (stop mode release by reset) data retention timing (stop mode release by standby release signal: interrupt signal) data retention supply current t srel t wait v dd stop instruction execution stop mode data retention mode halt mode operating mode standby release signal (interrupt request) v dddr t srel t wait v dd reset stop instruction execution stop mode data retention mode internal reset operation halt mode operating mode v dddr
55 m pd78062(a), 78063(a), 78064(a) interrupt input timing t intl t inth intp0?ntp5 reset input timing t rsl reset
56 m pd78062(a), 78063(a), 78064(a) 11. characteristic curves (reference values) i dd vs v dd (main system clock: 5.0 mhz) 0 2 1345678 pcc=b0h pcc=02h pcc=03h pcc=04h (t a = 25 c) 10.0 5.0 1.0 0.5 0.1 0.05 0.01 0.005 supply voltage v dd (v) supply current i dd (ma) 0.001 halt (x1 oscillation, xt1 oscillation) pcc=00h pcc=01h pcc=30h f xt = 32.768 khz f xx = 5.0 mhz halt stop (x1 stop, xt1 oscillation) (x1 stop, xt1 oscillation)
57 m pd78062(a), 78063(a), 78064(a) i dd vs v dd (main system clock: 2.5 mhz) 0 2 1345678 pcc=b0h pcc=02h pcc=03h pcc=04h (t a = 25 c) 10.0 5.0 1.0 0.5 0.1 0.05 0.01 0.005 supply voltage v dd (v) supply current i dd (ma) 0.001 halt (x1 oscillation, xt1 oscillation) pcc=00h pcc=01h pcc=30h f xt = 32.768 khz f xx = 2.5 mhz halt stop (x1 stop, xt1 oscillation) (x1 stop, xt1 oscillation)
58 m pd78062(a), 78063(a), 78064(a) 12. package drawings 100 pin plastic qfp (fine pitch) ( 14) item millimeters inches i j 0.5 (t.p.) 0.10 0.004 0.020 (t.p.) a note each lead centerline is located within 0.10 mm (0.004 inch) of its true position (t.p.) at maximum material condition. s a 16.0?.2 0.630?.008 b 14.0?.2 0.551 +0.009 ?.008 c 14.0?.2 0.551 +0.009 ?.008 d 16.0?.2 0.630?.008 f g 1.0 1.0 0.039 0.039 h 0.22 0.009?.002 p100gc-50-7ea-2 k 1.0?.2 0.039 +0.009 ?.008 l 0.5?.2 0.020 +0.008 ?.009 m 0.17 0.007 n 0.10 0.004 p 1.45 0.057 +0.05 ?.04 +0.03 ?.07 b c d j h i g f p n l k m q r detail of lead end q 0.125?.075 0.005?.003 r s 1.7 max. 55? 55? 0.067 max. +0.001 ?.003 m 1 25 26 50 100 76 75 51 remark dimensions and materials of es products are same as those of mass production product.
59 m pd78062(a), 78063(a), 78064(a) j n m p 80 81 50 100 pin plastic qfp (14 20) 100 1 31 30 51 g detail of lead end s 5 5 c d a b h q k l f m i p100gf-65-3ba1-2 item millimeters inches a b c d f g h i j k l 23.6 0.4 14.0 0.2 0.6 0.30 0.10 0.15 20.0 0.2 0.929 0.016 0.031 0.024 0.006 0.026 (t.p.) 0.795 note m n 0.10 0.15 1.8 0.2 0.65 (t.p.) 0.006 0.031 +0.009 ?.008 each lead centerline is located within 0.15 mm (0.006 inch) of its true position (t.p.) at maximum material condition. 0.012 0.551 0.8 0.2 0.071 p 2.7 0.106 0.693 0.016 17.6 0.4 0.8 +0.008 ?.009 q 0.1 0.1 0.004 0.004 s 3.0 max. 0.119 max. +0.10 ?.05 +0.009 ?.008 +0.004 ?.005 +0.009 ?.008 +0.004 ?.003 0.004 remark dimensions and materials of es products are same as mass production product.
60 m pd78062(a), 78063(a), 78064(a) 100 pin plastic lqfp (fine pitch) (14 14) item millimeters inches note each lead centerline is located within 0.08 mm (0.003 inch) of its true position (t.p.) at maximum material condition. s100gc-50-8eu f 1.00 0.039 b 14.00?.20 0.551 +0.009 ?.008 s 1.60 max. 0.063 max. l 0.50?.20 0.020 +0.008 ?.009 +0.009 ?.008 c 14.00?.20 0.551 +0.009 ?.008 a 16.00?.20 0.630?.008 g 1.00 0.039 h 0.22 0.009?.002 i 0.08 0.003 j 0.50 (t.p.) 0.020 (t.p.) k 1.00?.20 0.039 +0.009 ?.008 n 0.08 0.003 p 1.40?.05 0.055?.002 r3 3 +7 ? +7 ? d 16.00?.20 0.630?.008 m q r k m l j h i f g p n detail of lead end m 0.17 0.007 +0.001 ?.003 +0.03 ?.07 q 0.10?.05 0.004?.002 +0.05 ?.04 1 25 26 50 100 76 75 51 cd s a b remark dimensions and materials of es products are same as mass production product.
61 m pd78062(a), 78063(a), 78064(a) 13. recommended soldering conditions the m pd78062(a)/78063(a)/78064(a) should be soldered and mounted under the conditions recommended in the table below. for detail of recommended soldering conditions, refer to the information document semiconductor device mounting technology manual (c10535e) . for soldering methods and conditions other than those recommended below, contact our sales personnel. table 13-1. surface mounting type soldering conditions (1/2) (1) m pd78062gc(a)- -7ea : 100-pin plastic qfp (fine pitch) (14 14mm, resin thickness: 1.45 mm) m pd78063gc(a)- -7ea : 100-pin plastic qfp (fine pitch) (14 14mm, resin thickness: 1.45 mm) m pd78064gc(a)- -7ea : 100-pin plastic qfp (fine pitch) (14 14mm, resin thickness: 1.45 mm) package peak temperature: 235 c, duration: 30 sec. max. (at 210 c or above), number of times: twice max., time limit: 7 days note (thereafter 10 hours prebaking required at 125 c) baking cannot be applied to other than heat-resistant trays (magazine, taping, non- heat-resistant trays) when the product is wrapped. package peak temperature: 215 c, duration: 40 sec. (at 200 c or above), number of times: twice max., time limit: 7 days note (thereafter 10 hours prebaking required at 125 c) baking cannot be applied to other than heat-resistant trays (magazine, taping, non- heat-resistant trays) when the product is wrapped. pin temperature: 300 c max. duration: 3 sec. max. (per device side) recommended condition symbol soldering method soldering conditions infrared reflow vps partial heating ir35-107-2 vp15-107-2 note for the storage period after dry-pack decapsulation, storage conditions are max. 25 c, 65% rh. (2) m pd78062gf(a)- -3ba : 100-pin plastic qfp (14 20 mm) m pd78063gf(a)- -3ba : 100-pin plastic qfp (14 20 mm) m pd78064gf(a)- -3ba : 100-pin plastic qfp (14 20 mm) package peak temperature: 235 c, duration: 30 sec. max. (at 210 c or above), number of times: thrice max. package peak temperature: 215 c, duration: 40 sec. (at 200 c or above), number of times: thrice max. solder bath temperature: 260 c max., duration: 10 sec. max., number of times: once, preliminary heat temperature: 120 c max. (package surface temperature) pin temperature: 300 c max. duration: 3 sec. max. (per device side) recommended condition symbol soldering method soldering conditions ir35-00-3 vp15-00-3 ws60-00-1 infrared reflow vps wave soldering partial heating cautions 1. use of more than one soldering method should be avoided (except in the case of partial heating). 2. the m pd78062gc(a)- -8eu, 78063gc(a)- -8eu, and 78064gc(a)- -8eu are under planning. therefore, soldering conditions for these products have not been specified.
62 m pd78062(a), 78063(a), 78064(a) appendix a. development tools the following development tools are available for system development using m pd78062(a)/78063(a)/78064(a). language processing software ra78k/0 note 1, 2, 3, 4 cc78k/0 note 1, 2, 3, 4 df78064 note 1, 2, 3, 4 cc78k/0-l note 1, 2, 3 ,4 78k/0 series common assembler package 78k/0 series common c compiler package m pd78064 subseries device file 78k/0 series common c compiler library source file prom writing tools ie-78000-r ie-78000-r-a ie-78000-r-bk ie-78064-r-em note 8 ie-780308-r-em ie-78000-r-sv3 ie-70000-98-if-b ie-70000-98n-if ie70000-pc-if-b ep-78064gc-r ep-78064gf-r tgc-100sdw ev-9200gf-100 sm78k0 note 5, 6, 7 id78k0 note 4, 5, 6, 7 sd78k/0 note 1, 2 df78064 note 1, 2, 4, 5, 6, 7 78k/0 series common in-circuit emulator 78k/0 series common in-circuit emulator (for integrated debugger) 78k/0 series common break board m pd78064 subseries evaluation emulation board m pd780308 subseries common emulation board interface adapter and cable when ews is used as host machine (for ie-78000-r-a) interface adapter when pc-9800 series (except notebook type) is used as host machine (for ie- 78000-r-a) interface adapter and cable when notebook type pc-9800 series is used as host machine (for ie- 78000-r-a) interface adapter when ibm pc/at tm is used as host machine (ie-78000-r-a) m pd78064 subseries common emulation probes adapter to be mounted on a target system board made for 100-pin plastic qfp (gc-7ea, gc-8eu type) tgc-100sdw is a product from tokyo eletech corp. (tel (03) 5295-1661) when purchasing this product, please consult with our sales offices. socket to be mounted on a target system board made for 100-pin plastic qfp (gf-3ba type) 78k/0 series common system simulator ie-78000-r-a integrated dubugger ie-78000-r screen debugger m pd78064 subseries device file pg-1500 pa-78p0308gc (or pa-78p064gc) pa-78p0308gf (or pa-78p064gf) pa-78p0308kl-t pg-1500 controller notes 1, 2 prom programmer programmer adapters connected to pg-1500 pg-1500 control program debugging tools
63 m pd78062(a), 78063(a), 78064(a) fuzzy inference development support system notes 1. pc-9800 series (ms-dos tm ) based 2. ibm pc/at and compatible (pc dos tm /ibm dos tm /ms-dos) based 3. hp9000 series 300 tm (hp-ux tm ) based 4. hp9000 series 700 tm (hp-ux) based, sparcstation tm (sunos tm ) based, ews-4800 series (ews-ux/v) based 5. pc-9800 series (ms-dos + windows tm ) based. 6. ibm pc/at and compatible (pc dos/ibm dos/ms-dos + windows) based 7. news tm (news-os tm ) based 8. ie-78064-r-em is a maintenance product. fe9000 note 1 , fe9200 note 6 ft9080 note 1 , ft9085 note 2 fi78k/0 note 1, 2 fd78k/0 note 1, 2 fuzzy knowledge data creation tool translator fuzzy inference module fussy inference debugger remarks 1. for third party development tools, refer to the 78k/0 series selection guide (u11126e) . 2. ra78k/0, cc78k/0, sm78k0, id78k0, sd78k/0, and rx78k/0 are used in combination with df78064. real-time os rx78k/0 note 1, 2, 3, 4 mx78k0 note 1, 2, 3, 4 78k/0 series real-time os 78k/0 series os
64 m pd78062(a), 78063(a), 78064(a) appendix b. related documents device related documents document name document no. japanese english m pd78062(a), 78063(a) 78064(a) data sheet u10335j this document m pd78064, 78064y subseries user's manual u10105j u10105e 78k/0 series user's manual - instruction u12326j ieu-1372 78k/0 series instruction table u10903j 78k/0 series instruction set u10904j m pd78018f subseries special function register table iem-5568 78k/0 series application note fundamental (iii) iea-767 u10182e floating-point arithmetic program iea-718 iea-1289 development tools related documents (users manual) (1/2) document name document no. japanese english ra78k series assembler package operation eeu-809 eeu-1399 language eeu-815 eeu-1404 ra78k series structured assembler preprocessor eeu-817 eeu-1402 ra78k0 assembler package operation u11802j u11802e assembly language u11801j u11801e structured assembly language u11789j u11789e cc78k series c compiler operation eeu-656 eeu-1280 language eeu-655 eeu-1284 cc78k/0 c compiler operation u11517j u11517e language u11518j u11518e cc78k/0 c compiler application note programming know-how eea-618 eea-1208 cc78k series library source file u12322j ie-78000-r eeu-810 u11376e ie-78000-r-a u10057j u10057e ie-78000-r-bk eeu-867 eeu-1427 ie-78064-r-em eeu-905 eeu-1443 ie-780308-r-em u11362j u11362e ep-78064 eeu-934 eeu-1469 caution the contents of the above related documents are subject to change without notice. the latest documents should be used for design, etc.
65 m pd78062(a), 78063(a), 78064(a) development tools documents (user's manual) (2/2) document name document no. japanese english sm78k series system simulator external components user open u10092j u10092e interface sm78k0 system simulator windows based reference u10181j u10181e id78k0 integrated debugger ews based reference u11515j id78k0 integrated debugger pc based reference u11539j u11539e id78k0 integrated debugger windows based guide u11649j u11649e sd78k/0 screen debugger introduction eeu-852 u10539e pc-9800 series (ms-dos) based reference u10952j sd78k/0 screen debugger introduction eeu-5024 eeu-1414 ibm pc/at (pc dos) based reference u11279j u11279e embedded software documents (user's manual) document name document no. japanese english 78k/0 series real-time os fundamental u11537j installation u11536j 78k/0 series os mx78k0 fundamental u12257j fuzzy knowledge data creation tool eeu-829 eeu-1438 78k/0, 78k/ii, 87ad series fuzzy inference development support system eeu-862 eeu-1444 - translator 78k/0 series fuzzy inference development suport system eeu-858 eeu-1441 - fuzzy inference module 78k/0 series fuzzy inference development support system eeu-921 eeu-1458 - fuzzy inference debugger other documents document name document no. japanese english ic package manual c10943x semiconductor device mounting technology manual c10535j c10535e quality grades on nec semiconductor device c11531j c11531e nec semiconductor device reliability/quality control system c10983j c10983e electrostatic discharge (esd) test mem-539 guide to quality assurance for semiconductor device c11893j c11893e guide for products related to microcomputer: other companies u11416j caution the contents of the above related documents are subject to change without notice. the latest documents should be used for design, etc.
66 m pd78062(a), 78063(a), 78064(a) notes for cmos devices 1 precaution against esd for semiconductors note: strong electric field, when exposed to a mos device, can cause destruction of the gate oxide and ultimately degrade the device operation. steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. environmental control must be adequate. when it is dry, humidifier should be used. it is recommended to avoid using insulators that easily build static electricity. semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. all test and measurement tools including work bench and floor should be grounded. the operator should be grounded using wrist strap. semiconductor devices must not be touched with bare hands. similar precautions need to be taken for pw boards with semiconductor devices on it. 2 handling of unused input pins for cmos note: no connection for cmos device inputs can be cause of malfunction. if no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. cmos device behave differently than bipolar or nmos devices. input levels of cmos devices must be fixed high or low by using a pull-up or pull-down circuitry. each unused pin should be connected to v dd or gnd with a resistor, if it is considered to have a possibility of being an output pin. all handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 status before initialization of mos devices note: power-on does not necessarily define initial status of mos device. produc- tion process of mos does not define the initial operation status of the device. immediately after the power source is turned on, the devices with reset function have not yet been initialized. hence, power-on does not guarantee out-pin levels, i/o settings or contents of registers. device is not initialized until the reset signal is received. reset operation must be executed imme- diately after power-on for devices having reset function.
67 m pd78062(a), 78063(a), 78064(a) nec electronics inc. (u.s.) santa clara, california tel: 800-366-9782 fax: 800-729-9288 nec electronics (germany) gmbh duesseldorf, germany tel: 0211-65 03 02 fax: 0211-65 03 490 nec electronics (uk) ltd. milton keynes, uk tel: 01908-691-133 fax: 01908-670-290 nec electronics italiana s.r.1. milano, italy tel: 02-66 75 41 fax: 02-66 75 42 99 nec electronics hong kong ltd. hong kong tel: 2886-9318 fax: 2886-9022/9044 nec electronics hong kong ltd. seoul branch seoul, korea tel: 02-528-0303 fax: 02-528-4411 nec electronics singapore pte. ltd. united square, singapore 1130 tel: 253-8311 fax: 250-3583 nec electronics taiwan ltd. taipei, taiwan tel: 02-719-2377 fax: 02-719-5951 nec do brasil s.a. sao paulo-sp, brasil tel: 011-889-1680 fax: 011-889-1689 nec electronics (germany) gmbh benelux office eindhoven, the netherlands tel: 040-2445845 fax: 040-2444580 nec electronics (france) s.a. velizy-villacoublay, france tel: 01-30-67 58 00 fax: 01-30-67 58 99 nec electronics (france) s.a. spain office madrid, spain tel: 01-504-2787 fax: 01-504-2860 nec electronics (germany) gmbh scandinavia office taeby, sweden tel: 08-63 80 820 fax: 08-63 80 388 regional information some information contained in this document may vary from country to country. before using any nec product in your application, please contact the nec office in your country to obtain a list of authorized representatives and distributors. they will verify: ? device availability ? ordering information ? product release schedule ? availability of related technical literature ? development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, ac supply voltages, and so forth) ? network requirements in addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country. j96. 8
m pd78062(a), 78063(a), 78064(a) fip is a registered trademark of nec corporation. iebus is a trademark of nec corporation. ms-dos and windows are either registered trademarks or trademarks of microsoft corporation in the united states and/or other countries. ibm-dos, pc/at, and pc dos are trademarks of ibm corporation. hp9000 series 300, hp9000 series 700, and hp-ux are trademarks of hewlett-packard company. sparcstation is a trademark of sparc international, inc. sunos is a trademark of sun microsystems, inc. news and news-os are trademarks of sony corporation. some of related document may be preliminary, but is not marked as such. please keep this in mind as you refer to this information. no part of this document may be copied or reproduced in any form or by any means without the prior written consent of nec corporation. nec corporation assumes no responsibility for any errors which may appear in this document. nec corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. no license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of nec corporation or others. while nec corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. to minimize risks of damage or injury to persons or property arising from a defect in an nec semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. nec devices are classified into the following three quality grades: "standard", "special", and "specific". the specific quality grade applies only to devices developed based on a customer designated "quality assurance program" for a specific application. the recommended applications of a device depend on its quality grade, as indicated below. customers must check the quality grade of each device before using it in a particular application. standard: computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots special: transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) specific: aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. the quality grade of nec devices is "standard" unless otherwise specified in nec's data sheets or data books. if customers intend to use nec devices for applications other than those specified for standard quality grade, they should contact an nec sales representative in advance. anti-radioactive design is not implemented in this product. m4 96.5 the export of this product from japan is regulated by the japanese government. to export this product may be prohibited without governmental license, the need for which must be judged by the customer. the export or re-export of this product from a country other than japan may also be prohibited without a license from that country. please call an nec sales representative.

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